Applications such as neuromorphic computing, graphical analytics and some classical computing paradigms such as central processing units (CPUs) benefit from dense on-chip memory. On-chip memory for such logic chips is typically six transistor (6T) or eight transistor (8T) static random-access memory (SRAM). Such 6T and 8T SRAM include six and eight transistors, respectively, per cell. The 6T and 8T cells consume large areas. This limits the total number of memory cells that can be accommodated on-chip. Other memory, such as denser nonvolatile memory (NVM) elements and dynamic RAM (DRAM) may require high programming voltages or high refresh power. Consequently, such memories may also be difficult to integrate on a logic die.
Accordingly, what is desired are improved memory cells that may be integrated into logic chips.